SK Hynix Sandisk HBF Standard Unveiled: 512GB Capacity and 3TB/s Bandwidth for AI Inference Memory

The Memory Wall Just Got a New Layer: High Bandwidth Flash Specs Arrive

SK hynix and Sandisk publish the first open HBF technical specification, targeting up to 512 GB and 3 TB/s to ease the capacity-bandwidth gap that is constraining large-scale AI inference.

August 4, 2026 · 6 min read

Quick Highlights

• First HBF standard released via Open Compute Project roughly six months after the consortium launched in February 2026.
• Maximum capacity specified at 512 GB using 8-high or 16-high specialized NAND die stacks.
• Bandwidth grades range from approximately 0.4 TB/s to 3.0 TB/s.
• UCIe interconnect adopted to enable flexible attachment to GPUs, CPUs and other accelerators.
• Google and Tenstorrent listed among consortium participants contributing to validation.

On August 4, 2026, SK hynix and Sandisk formally released the first technical specification for High Bandwidth Flash (HBF) through the Open Compute Project. The document defines a new memory tier explicitly positioned between high-bandwidth memory (HBM) and conventional solid-state drives, aiming to supply AI inference systems with larger near-compute capacity while delivering substantially higher bandwidth than traditional storage.

The release coincides with the opening of the Future of Memory and Storage 2026 conference in Santa Clara, California. It marks the first concrete industry standard produced by the HBF consortium after its February kickoff, itself building on an earlier bilateral standardization partnership. For operators running large language models and agentic workloads, the specification offers a concrete path toward reducing the growing mismatch between accelerator compute and available memory capacity and bandwidth.

Why a New Memory Tier Became Necessary

AI infrastructure has long relied on HBM for the highest-bandwidth, lowest-latency working set and on SSDs or other storage for bulk capacity. As models grow and inference demand expands, that binary division creates a costly gap: HBM remains expensive and capacity-constrained, while SSDs cannot feed data to accelerators fast enough for many real-time or high-throughput inference scenarios.

HBF is designed to occupy the middle ground. It uses stacked NAND flash dies engineered for higher interface speeds rather than conventional 3D NAND packages. The result is non-volatile capacity measured in hundreds of gigabytes paired with bandwidth that, at the top grade, exceeds a single HBM4 stack’s roughly 2 TB/s figure, although latency characteristics will differ.

Core Technical Specifications

The published specification covers two primary stack configurations—8-high and 16-high NAND dies—supporting packages up to 512 GB. Bandwidth is organized into three performance grades spanning approximately 0.4 TB/s to 3.0 TB/s. The interconnect standard is Universal Chiplet Interconnect Express (UCIe), chosen to allow HBF modules to attach to a range of processors without proprietary lock-in.

Additional guidance addresses electrical interfaces, packaging, reliability expectations, and basic software operations for reads and writes. Because the specification was released under the Open Compute Project framework, the technical details are openly available to any company that wishes to design compatible products or systems.

Attribute	HBF Specification	Typical Context
Max Capacity	512 GB (8-Hi / 16-Hi stacks)	Between HBM and enterprise SSD
Bandwidth Range	\~0.4 – 3.0 TB/s	Top grade exceeds single HBM4 stack bandwidth
Interconnect	UCIe	Enables GPU/CPU/accelerator attachment
Volatility	Non-volatile (NAND-based)	Retains data without power
Primary Use Case	AI inference capacity tier	Complements, does not replace, HBM

Industry Participation and Timeline

Google and AI-chip developer Tenstorrent joined the consortium during the standardization process and contributed to technical validation. SK hynix has indicated that the group will continue refining the standard and expanding ecosystem support under open collaboration. Sampling of first inference devices using HBF technology has been projected for early 2027 by company executives in earlier comments.

SK hynix also used the FMS 2026 platform to showcase related memory advances, including its tenth-generation 375-layer 4D NAND, described as offering approximately 2.5 times higher power efficiency relative to prior generations.

Practical Implications for AI Accelerators

For system designers, HBF provides a standardized way to add hundreds of gigabytes of relatively fast, non-volatile memory close to the compute fabric. A 500-billion-parameter model, for example, could keep a larger fraction of its weights or intermediate states in this tier rather than shuttling data across slower storage or oversubscribing scarce HBM. The UCIe interface is intended to simplify integration across heterogeneous platforms rather than requiring a single vendor’s proprietary memory controller.

Power efficiency and total cost of ownership are repeatedly cited as secondary benefits. Because HBF targets inference rather than the highest-performance training workloads, it can be deployed where capacity and sustained bandwidth matter more than absolute minimum latency.

Broader industry context: Memory has become one of the most constrained resources in the current AI build-out. Standardization efforts such as HBF reflect a shift from pure proprietary differentiation toward shared technical frameworks that can accelerate adoption and reduce integration risk for hyperscalers, AI chip startups, and enterprise system builders alike. Whether HBF achieves volume deployment will depend on actual silicon performance, software stack maturity, and pricing relative to expanded HBM and next-generation storage options.

Frequently Asked Questions

HBF is a proposed new memory tier that combines stacked NAND flash capacity with a high-speed interface. It sits between HBM (very high bandwidth, limited capacity, volatile) and conventional SSDs (high capacity, lower bandwidth). The goal is to give AI inference systems more near-compute memory without the full cost and power profile of additional HBM stacks.

The top HBF bandwidth grade of approximately 3 TB/s exceeds the roughly 2 TB/s of a single HBM4 stack. However, latency, power characteristics, and sustained performance under real workloads will differ because HBF is flash-based rather than DRAM-based. It is intended as a complementary tier, not a direct HBM replacement.

Releasing under OCP makes the technical details openly available, encouraging multiple vendors to design compatible products and systems. The consortium approach, which now includes Google and Tenstorrent, aims to establish HBF as a de-facto industry standard rather than a proprietary interface controlled by one or two companies.

The specification itself is an initial technical framework, not finished silicon. Company commentary has pointed to sampling of first inference devices around early 2027. Full commercial availability and volume production will depend on further engineering, validation, and ecosystem software support.

No. HBF is explicitly positioned as an intermediate tier. High-performance training and the hottest working sets will continue to rely on HBM. Bulk cold storage will still use SSDs or other media. HBF targets the growing set of inference workloads that need more capacity than HBM can economically provide and more bandwidth than traditional storage can deliver.

Final Thoughts

The publication of the first HBF specification is a concrete engineering response to a well-documented constraint in AI infrastructure: the widening gap between accelerator compute capability and the memory systems that feed it. By defining capacity, bandwidth grades, and an open interconnect in a single reference document, SK hynix and Sandisk have given system architects a shared target to design against.

Whether HBF becomes a widely deployed layer will be determined by silicon results, software enablement, and economics over the next 18–24 months. For now, the standard itself represents a measurable step toward treating AI memory as a multi-tier, interoperable stack rather than a binary choice between scarce high-performance DRAM and slower bulk storage.

Sources: SK hynix official newsroom (August 4, 2026), Sandisk investor announcement, Tom’s Hardware, The Korea Herald, Businesskorea, Open Compute Project framework documentation.